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Verification Techniques For System Level Design

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High Level Verification

High Level Verification Book
Author : Sudipta Kundu,Sorin Lerner,Rajesh K. Gupta
Publisher : Springer Science & Business Media
Release : 2011-05-18
ISBN : 9781441993595
Language : En, Es, Fr & De

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Book Description :

Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing. This book focuses on high-level verification, presenting a design methodology that relies upon advances in synthesis techniques as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL.

ESL Design and Verification

ESL Design and Verification Book
Author : Grant Martin,Brian Bailey,Andrew Piziali
Publisher : Elsevier
Release : 2010-07-27
ISBN : 9780080488837
Language : En, Es, Fr & De

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Book Description :

Visit the authors' companion site! http://www.electronicsystemlevel.com/ - Includes interactive forum with the authors! Electronic System Level (ESL) design has mainstreamed – it is now an established approach at most of the world’s leading system-on-chip (SoC) design companies and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with ‘no links to implementation’, ESL is evolving into a set of complementary methodologies that enable embedded system design, verification and debug through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on-board, and entire multi-board systems. This book arises from experience the authors have gained from years of work as industry practitioners in the Electronic System Level design area; they have seen "SLD" or "ESL" go through many stages and false starts, and have observed that the shift in design methodologies to ESL is finally occurring. This is partly because of ESL technologies themselves are stabilizing on a useful set of languages being standardized (SystemC is the most notable), and use models are being identified that are beginning to get real adoption. ESL DESIGN & VERIFICATION offers a true prescriptive guide to ESL that reviews its past and outlines the best practices of today. Table of Contents CHAPTER 1: WHAT IS ESL? CHAPTER 2: TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL CHAPTER 3: EVOLUTION OF ESL DEVELOPMENT CHAPTER 4: WHAT ARE THE ENABLERS OF ESL? CHAPTER 5: ESL FLOW CHAPTER 6: SPECIFICATIONS AND MODELING CHAPTER 7: PRE-PARTITIONING ANALYSIS CHAPTER 8: PARTITIONING CHAPTER 9: POST-PARTITIONING ANALYSIS AND DEBUG CHAPTER 10: POST-PARTITIONING VERIFICATION CHAPTER 11: HARDWARE IMPLEMENTATION CHAPTER 12: SOFTWARE IMPLEMENTATION CHAPTER 13: USE OF ESL FOR IMPLEMENTATION VERIFICATION CHAPTER 14: RESEARCH, EMERGING AND FUTURE PROSPECTS APPENDIX: LIST OF ACRONYMS * Provides broad, comprehensive coverage not available in any other such book * Massive global appeal with an internationally recognised author team * Crammed full of state of the art content from notable industry experts

Verification Techniques for System Level Design

Verification Techniques for System Level Design Book
Author : Masahiro Fujita,Indradeep Ghosh,Mukul Prasad
Publisher : Morgan Kaufmann
Release : 2010-07-27
ISBN : 9780080553139
Language : En, Es, Fr & De

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Book Description :

This book will explain how to verify SoC (Systems on Chip) logic designs using “formal and “semiformal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in “functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity. For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs. • First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs. • Formal verification of high-level designs (RTL or higher). • Verification techniques are discussed with associated system-level design methodology.

Embedded System Design

Embedded System Design Book
Author : Daniel D. Gajski,Samar Abdi,Andreas Gerstlauer,Gunar Schirner
Publisher : Springer Science & Business Media
Release : 2009-08-14
ISBN : 1441905049
Language : En, Es, Fr & De

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Book Description :

Embedded System Design: Modeling, Synthesis and Verification introduces a model-based approach to system level design. It presents modeling techniques for both computation and communication at different levels of abstraction, such as specification, transaction level and cycle-accurate level. It discusses synthesis methods for system level architectures, embedded software and hardware components. Using these methods, designers can develop applications with high level models, which are automatically translatable to low level implementations. This book, furthermore, describes simulation-based and formal verification methods that are essential for achieving design confidence. The book concludes with an overview of existing tools along with a design case study outlining the practice of embedded system design. Specifically, this book addresses the following topics in detail: . System modeling at different abstraction levels . Model-based system design . Hardware/Software codesign . Software and Hardware component synthesis . System verification This book is for groups within the embedded system community: students in courses on embedded systems, embedded application developers, system designers and managers, CAD tool developers, design automation, and system engineering.

System on a Chip Verification

System on a Chip Verification Book
Author : Prakash Rashinkar,Peter Paterson,Leena Singh
Publisher : Springer Science & Business Media
Release : 2001
ISBN : 0792372794
Language : En, Es, Fr & De

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Book Description :

System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application. System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter: Explanation of the objective involved in performing verification after a given design step; Features of options available; When to use a particular option; How to select an option; and Limitations of the option. This exciting new book will be of interest to all designers and test professionals.

Formal Methods and Models for System Design

Formal Methods and Models for System Design Book
Author : Rajesh Gupta,Paul Le Guernic,Sandeep Kumar Shukla,Jean-Pierre Talpin
Publisher : Springer Science & Business Media
Release : 2004-10-01
ISBN : 9781402080517
Language : En, Es, Fr & De

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Book Description :

Perhaps nothing characterizes the inherent heterogeneity in embedded sys tems than the ability to choose between hardware and software implementations of a given system function. Indeed, most embedded systems at their core repre sent a careful division and design of hardware and software parts of the system To do this task effectively, models and methods are necessary functionality. to capture application behavior, needs and system implementation constraints. Formal modeling can be valuable in addressing these tasks. As with most engineering domains, co-design practice defines the state of the it seeks to add new capabilities in system conceptualization, mod art, though eling, optimization and implementation. These advances -particularly those related to synthesis and verification tasks -direct1y depend upon formal under standing of system behavior and performance measures. Current practice in system modeling relies upon exploiting high-level programming frameworks, such as SystemC, EstereI, to capture design at increasingly higher levels of ab straction and attempts to reduce the system implementation task. While raising the abstraction levels for design and verification tasks, to be really useful, these approaches must also provide for reuse, adaptation of the existing intellectual property (IP) blocks.

Quality Driven SystemC Design

Quality Driven SystemC Design Book
Author : Daniel Große,Rolf Drechsler
Publisher : Springer Science & Business Media
Release : 2009-12-02
ISBN : 9048136318
Language : En, Es, Fr & De

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Book Description :

A quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results.

Functional Verification of Programmable Embedded Architectures

Functional Verification of Programmable Embedded Architectures Book
Author : Prabhat Mishra,Nikil D. Dutt
Publisher : Springer Science & Business Media
Release : 2005-07
ISBN : 9780387261430
Language : En, Es, Fr & De

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Book Description :

Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many existing validation techniques employ a bottom-up approach to design verification, where the functionality of an existing architecture is, in essence, reverse-engineered from its implementation. Traditional validation techniques employ different reference models depending on the abstraction level and verification task, resulting in potential inconsistencies between multiple reference models. This book presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect’s knowledge about the behavior of the design through architecture specification using an Architecture Description Language (ADL). The authors also address two fundamental challenges in functional verification: lack of a golden reference model, and lack of a comprehensive functional coverage metric. Functional Verification of Programmable Embedded Architectures: A Top-Down Approach is designed for students, researchers, CAD tool developers, designers, and managers interested in the development of tools, techniques and methodologies for system-level design, microprocessor validation, design space exploration and functional verification of embedded systems.

System Level Design with Net Technology

System Level Design with  Net Technology Book
Author : El Mostapha Aboulhamid,Frederic Rousseau
Publisher : CRC Press
Release : 2018-10-03
ISBN : 9781439812129
Language : En, Es, Fr & De

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Book Description :

The first book to harness the power of .NET for system design, System Level Design with .NET Technology constitutes a software-based approach to design modeling verification and simulation. World class developers, who have been at the forefront of system design for decades, explain how to tap into the power of this dynamic programming environment for more effective and efficient management of metadata—and introspection and interoperability between tools. Using readily available technology, the text details how to capture constraints and requirements at high levels and describes how to percolate them during the refinement process. Departing from proprietary environments built around System Verilog and VHDL, this cutting-edge reference includes an open source environment (ESys.NET) that readers can use to experiment with new ideas, algorithms, and design methods; and to expand the capabilities of their current tools. It also covers: Modeling and simulation—including requirements specification, IP reuse, and applications of design patterns to hardware/software systems Simulation and validation—including transaction-based models, accurate simulation at cycle and transaction levels, cosimulation and acceleration technique, as well as timing specification and validation Practical use of the ESys.NET environment Worked examples, end of chapter references, and the ESys.NET implementation test bed make this the ideal resource for system engineers and students looking to maximize their embedded system designs.

High level Verification of System Designs

High level Verification of System Designs Book
Author : Sudipta Kundu
Publisher : Unknown
Release : 2009
ISBN : 0987650XXX
Language : En, Es, Fr & De

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Book Description :

Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. The growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far has been on traditional testing techniques such as random testing and scenario-based testing. This dissertation focuses on high-level verification of system designs. We envision a design methodology that relies upon advances in synthesis techniques as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. Our work addresses verification of specific properties in high-level languages as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. Our work falls into two categories: (a) methods for verifying properties of high-level designs and (b) methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Taken together, these two parts guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL. By performing verification on the high-level design, where the design description is smaller in size and the design intent information is easier to extract, and then checking that all refinement steps are correct, we expand hardware development methodology to provide strong and expressive guarantees that are difficult to achieve by directly analyzing the low-level RTL code. Our techniques for high-level verification have been implemented in a framework, which consists of four tools, namely Satya, Candor, Surya, and PEC. We demonstrate the value of our techniques by verifying various industrial strength designs and a complex CAD-tool package called Spark.

System level Test and Validation of Hardware Software Systems

System level Test and Validation of Hardware Software Systems Book
Author : Matteo Sonza Reorda,Zebo Peng,Massimo Violante
Publisher : Springer
Release : 2010-11-10
ISBN : 9781849969536
Language : En, Es, Fr & De

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Book Description :

New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers. SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue. This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: modeling of bugs and defects; stimulus generation for validation and test purposes (including timing errors; design for testability.

Design Methods and Applications for Distributed Embedded Systems

Design Methods and Applications for Distributed Embedded Systems Book
Author : Bernd Kleinjohann,Guang R. Gao,Hermann Kopetz,Lisa Kleinjohann,Achim Rettberg
Publisher : Springer
Release : 2006-04-11
ISBN : 1402081499
Language : En, Es, Fr & De

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Book Description :

The IFIP TC-10 Working Conference on Distributed and Parallel Embedded Systems (DIPES 2004) brings together experts from industry and academia to discuss recent developments in this important and growing field in the splendid city of Toulouse, France. The ever decreasing price/performance ratio of microcontrollers makes it economically attractive to replace more and more conventional mechanical or electronic control systems within many products by embedded real-time computer systems. An embedded real-time computer system is always part of a well-specified larger system, which we call an intelligent product. Although most intelligent products start out as stand-alone units, many of them are required to interact with other systems at a later stage. At present, many industries are in the middle of this transition from stand-alone products to networked embedded systems. This transition requires reflection and architecting: The complexity of the evolving distributed artifact can only be controlled, if careful planning and principled design methods replace the - hoc engineering of the first version of many standalone embedded products.

System Level Design from HW SW to Memory for Embedded Systems

System Level Design from HW SW to Memory for Embedded Systems Book
Author : Marcelo Götz,Gunar Schirner,Marco Aurélio Wehrmeister,Mohammad Abdullah Al Faruque,Achim Rettberg
Publisher : Springer
Release : 2018-04-16
ISBN : 3319900234
Language : En, Es, Fr & De

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Book Description :

This book constitutes the refereed proceedings of the 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, held in Foz do Iguaçu, Brazil, in November 2015. The 18 full revised papers presented were carefully reviewed and selected from 25 submissions. The papers present a broad discussion on the design, analysis and verification of embedded and cyber-physical systems including design methodologies, verification, performance analysis, and real-time systems design. They are organized in the following topical sections: cyber-physical systems, system-level design; multi/many-core system design; memory system design; and embedded HW/SW design and applications.

System Level Design Techniques for Energy Efficient Embedded Systems

System Level Design Techniques for Energy Efficient Embedded Systems Book
Author : Marcus T. Schmitz,Bashir M. Al-Hashimi,Petru Eles
Publisher : Springer Science & Business Media
Release : 2004
ISBN : 9781402077500
Language : En, Es, Fr & De

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Book Description :

"System-Level Design Techniques for Energy-Efficient Embedded Systems will be of interest to advanced undergraduates, graduate students, and designers."--Jacket.

Embedded System Design

Embedded System Design Book
Author : Daniel D. Gajski,Samar Abdi,Andreas Gerstlauer,Gunar Schirner
Publisher : Springer
Release : 2014-11-26
ISBN : 9781489985309
Language : En, Es, Fr & De

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Book Description :

Embedded System Design: Modeling, Synthesis and Verification introduces a model-based approach to system level design. It presents modeling techniques for both computation and communication at different levels of abstraction, such as specification, transaction level and cycle-accurate level. It discusses synthesis methods for system level architectures, embedded software and hardware components. Using these methods, designers can develop applications with high level models, which are automatically translatable to low level implementations. This book, furthermore, describes simulation-based and formal verification methods that are essential for achieving design confidence. The book concludes with an overview of existing tools along with a design case study outlining the practice of embedded system design. Specifically, this book addresses the following topics in detail: . System modeling at different abstraction levels . Model-based system design . Hardware/Software codesign . Software and Hardware component synthesis . System verification This book is for groups within the embedded system community: students in courses on embedded systems, embedded application developers, system designers and managers, CAD tool developers, design automation, and system engineering.

VLSI Design and Test for Systems Dependability

VLSI Design and Test for Systems Dependability Book
Author : Shojiro Asai
Publisher : Springer
Release : 2018-07-20
ISBN : 4431565949
Language : En, Es, Fr & De

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Book Description :

This book discusses the new roles that the VLSI (very-large-scale integration of semiconductor circuits) is taking for the safe, secure, and dependable design and operation of electronic systems. The book consists of three parts. Part I, as a general introduction to this vital topic, describes how electronic systems are designed and tested with particular emphasis on dependability engineering, where the simultaneous assessment of the detrimental outcome of failures and cost of their containment is made. This section also describes the related research project “Dependable VLSI Systems,” in which the editor and authors of the book were involved for 8 years. Part II addresses various threats to the dependability of VLSIs as key systems components, including time-dependent degradations, variations in device characteristics, ionizing radiation, electromagnetic interference, design errors, and tampering, with discussion of technologies to counter those threats. Part III elaborates on the design and test technologies for dependability in such applications as control of robots and vehicles, data processing, and storage in a cloud environment and heterogeneous wireless telecommunications. This book is intended to be used as a reference for engineers who work on the design and testing of VLSI systems with particular attention to dependability. It can be used as a textbook in graduate courses as well. Readers interested in dependable systems from social and industrial–economic perspectives will also benefit from the discussions in this book.

Reconfigurable System Design and Verification

Reconfigurable System Design and Verification Book
Author : Pao-Ann Hsiung,Marco D. Santambrogio,Chun-Hsian Huang
Publisher : CRC Press
Release : 2018-10-08
ISBN : 1351834924
Language : En, Es, Fr & De

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Book Description :

Reconfigurable systems have pervaded nearly all fields of computation and will continue to do so for the foreseeable future. Reconfigurable System Design and Verification provides a compendium of design and verification techniques for reconfigurable systems, allowing you to quickly search for a technique and determine if it is appropriate to the task at hand. It bridges the gap between the need for reconfigurable computing education and the burgeoning development of numerous different techniques in the design and verification of reconfigurable systems in various application domains. The text explains topics in such a way that they can be immediately grasped and put into practice. It starts with an overview of reconfigurable computing architectures and platforms and demonstrates how to develop reconfigurable systems. This sets up the discussion of the hardware, software, and system techniques that form the core of the text. The authors classify design and verification techniques into primary and secondary categories, allowing the appropriate ones to be easily located and compared. The techniques discussed range from system modeling and system-level design to co-simulation and formal verification. Case studies illustrating real-world applications, detailed explanations of complex algorithms, and self-explaining illustrations add depth to the presentation. Comprehensively covering all techniques related to the hardware-software design and verification of reconfigurable systems, this book provides a single source for information that otherwise would have been dispersed among the literature, making it very difficult to search, compare, and select the technique most suitable. The authors do it all for you, making it easy to find the techniques that fit your system requirements, without having to surf the net or digital libraries to find the candidate techniques and compare them yourself.

Low Power Design with High Level Power Estimation and Power Aware Synthesis

Low Power Design with High Level Power Estimation and Power Aware Synthesis Book
Author : Sumit Ahuja,Avinash Lakshminarayana,Sandeep Kumar Shukla
Publisher : Springer Science & Business Media
Release : 2011-10-22
ISBN : 9781461408727
Language : En, Es, Fr & De

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Book Description :

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

System on a Chip Verification

System on a Chip Verification Book
Author : Prakash Rashinkar,Peter Paterson,Leena Singh
Publisher : Springer
Release : 2013-04-23
ISBN : 9781475774689
Language : En, Es, Fr & De

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Book Description :

This is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign-off. All the verification aspects in this exciting new book are illustrated with a single reference design for Bluetooth application.

Languages for Embedded Systems and their Applications

Languages for Embedded Systems and their Applications Book
Author : Martin Radetzki
Publisher : Springer Science & Business Media
Release : 2009-05-24
ISBN : 140209714X
Language : En, Es, Fr & De

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Book Description :

Embedded systems take over complex control and data processing tasks in diverse application ?elds such as automotive, avionics, consumer products, and telec- munications. They are the primary driver for improving overall system safety, ef?ciency, and comfort. The demand for further improvement in these aspects can only be satis?ed by designing embedded systems of increasing complexity, which in turn necessitates the development of new system design methodologies based on speci?cation, design, and veri?cation languages. The objective of the book at hand is to provide researchers and designers with an overview of current research trends, results, and application experiences in c- puter languages for embedded systems. The book builds upon the most relevant contributions to the 2008 conference Forum on Design Languages (FDL), the p- mier international conference specializing in this ?eld. These contributions have been selected based on the results of reviews provided by leading experts from - search and industry. In many cases, the authors have improved their original work by adding breadth, depth, or explanation.