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Architecture Design For Soft Errors

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Architecture Design for Soft Errors

Architecture Design for Soft Errors Book
Author : Shubu Mukherjee
Publisher : Morgan Kaufmann
Release : 2011-08-29
ISBN : 9780080558325
Language : En, Es, Fr & De

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Book Description :

Architecture Design for Soft Errors provides a comprehensive description of the architectural techniques to tackle the soft error problem. It covers the new methodologies for quantitative analysis of soft errors as well as novel, cost-effective architectural techniques to mitigate them. To provide readers with a better grasp of the broader problem definition and solution space, this book also delves into the physics of soft errors and reviews current circuit and software mitigation techniques. There are a number of different ways this book can be read or used in a course: as a complete course on architecture design for soft errors covering the entire book; a short course on architecture design for soft errors; and as a reference book on classical fault-tolerant machines. This book is recommended for practitioners in semi-conductor industry, researchers and developers in computer architecture, advanced graduate seminar courses on soft errors, and (iv) as a reference book for undergraduate courses in computer architecture. Helps readers build-in fault tolerance to the billions of microchips produced each year, all of which are subject to soft errors Shows readers how to quantify their soft error reliability Provides state-of-the-art techniques to protect against soft errors

Soft Errors

Soft Errors Book
Author : Jean-Luc Autran,Daniela Munteanu
Publisher : CRC Press
Release : 2015-02-25
ISBN : 146659084X
Language : En, Es, Fr & De

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Book Description :

Soft errors are a multifaceted issue at the crossroads of applied physics and engineering sciences. Soft errors are by nature multiscale and multiphysics problems that combine not only nuclear and semiconductor physics, material sciences, circuit design, and chip architecture and operation, but also cosmic-ray physics, natural radioactivity issues, particle detection, and related instrumentation. Soft Errors: From Particles to Circuits addresses the problem of soft errors in digital integrated circuits subjected to the terrestrial natural radiation environment—one of the most important primary limits for modern digital electronic reliability. Covering the fundamentals of soft errors as well as engineering considerations and technological aspects, this robust text: Discusses the basics of the natural radiation environment, particle interactions with matter, and soft-error mechanisms Details instrumentation developments in the fields of environment characterization, particle detection, and real-time and accelerated tests Describes the latest computational developments, modeling, and simulation strategies for the soft error-rate estimation in digital circuits Explores trends for future technological nodes and emerging devices Soft Errors: From Particles to Circuits presents the state of the art of this complex subject, providing comprehensive knowledge of the complete chain of the physics of soft errors. The book makes an ideal text for introductory graduate-level courses, offers academic researchers a specialized overview, and serves as a practical guide for semiconductor industry engineers or application engineers.

Soft Error Reliability of VLSI Circuits

Soft Error Reliability of VLSI Circuits Book
Author : Behnam Ghavami,Mohsen Raji
Publisher : Springer Nature
Release : 2020-11-14
ISBN : 3030516105
Language : En, Es, Fr & De

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Book Description :

This book is intended for readers who are interested in the design of robust and reliable electronic digital systems. The authors cover emerging trends in design of today’s reliable electronic systems which are applicable to safety-critical applications, such as automotive or healthcare electronic systems. The emphasis is on modeling approaches and algorithms for analysis and mitigation of soft errors in nano-scale CMOS digital circuits, using techniques that are the cornerstone of Computer Aided Design (CAD) of reliable VLSI circuits. The authors introduce software tools for analysis and mitigation of soft errors in electronic systems, which can be integrated easily with design flows. In addition to discussing soft error aware analysis techniques for combinational logic, the authors also describe new soft error mitigation strategies targeting commercial digital circuits. Coverage includes novel Soft Error Rate (SER) analysis techniques such as process variation aware SER estimation and GPU accelerated SER analysis techniques, in addition to SER reduction methods such as gate sizing and logic restructuring based SER techniques.

Resilient Architecture Design for Voltage Variation

Resilient Architecture Design for Voltage Variation Book
Author : Vijay Janapa Reddi,Meeta Sharma Gupta
Publisher : Morgan & Claypool Publishers
Release : 2013-05-01
ISBN : 1608456382
Language : En, Es, Fr & De

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Book Description :

Shrinking feature size and diminishing supply voltage are making circuits sensitive to supply voltage fluctuations within the microprocessor, caused by normal workload activity changes. If left unattended, voltage fluctuations can lead to timing violations or even transistor lifetime issues that degrade processor robustness. Mechanisms that learn to tolerate, avoid, and eliminate voltage fluctuations based on program and microarchitectural events can help steer the processor clear of danger, thus enabling tighter voltage margins that improve performance or lower power consumption. We describe the problem of voltage variation and the factors that influence this variation during processor design and operation. We also describe a variety of runtime hardware and software mitigation techniques that either tolerate, avoid, and/or eliminate voltage violations. We hope processor architects will find the information useful since tolerance, avoidance, and elimination are generalizable constructs that can serve as a basis for addressing other reliability challenges as well. Table of Contents: Introduction / Modeling Voltage Variation / Understanding the Characteristics of Voltage Variation / Traditional Solutions and Emerging Solution Forecast / Allowing and Tolerating Voltage Emergencies / Predicting and Avoiding Voltage Emergencies / Eliminiating Recurring Voltage Emergencies / Future Directions on Resiliency

FPGAs and Parallel Architectures for Aerospace Applications

FPGAs and Parallel Architectures for Aerospace Applications Book
Author : Fernanda Kastensmidt,Paolo Rech
Publisher : Springer
Release : 2015-12-07
ISBN : 3319143522
Language : En, Es, Fr & De

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Book Description :

This book introduces the concepts of soft errors in FPGAs, as well as the motivation for using commercial, off-the-shelf (COTS) FPGAs in mission-critical and remote applications, such as aerospace. The authors describe the effects of radiation in FPGAs, present a large set of soft-error mitigation techniques that can be applied in these circuits, as well as methods for qualifying these circuits under radiation. Coverage includes radiation effects in FPGAs, fault-tolerant techniques for FPGAs, use of COTS FPGAs in aerospace applications, experimental data of FPGAs under radiation, FPGA embedded processors under radiation and fault injection in FPGAs. Since dedicated parallel processing architectures such as GPUs have become more desirable in aerospace applications due to high computational power, GPU analysis under radiation is also discussed.

Design of Soft Error Robust High Speed 64 bit Logarithmic Adder

Design of Soft Error Robust High Speed 64 bit Logarithmic Adder Book
Author : Jaspal Singh Shah
Publisher :
Release : 2008
ISBN :
Language : En, Es, Fr & De

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Book Description :

Continuous scaling of the transistor size and reduction of the operating voltage have led to a significant performance improvement of integrated circuits. However, the vulnerability of the scaled circuits to transient data upsets or soft errors, which are caused by alpha particles and cosmic neutrons, has emerged as a major reliability concern. In this thesis, we have investigated the effects of soft errors in combinational circuits and proposed soft error detection techniques for high speed adders. In particular, we have proposed an area-efficient 64-bit soft error robust logarithmic adder (SRA). The adder employs the carry merge Sklansky adder architecture in which carries are generated every 4 bits. Since the particle-induced transient, which is often referred to as a single event transient (SET) typically lasts for 100~200 ps, the adder uses time redundancy by sampling the sum outputs twice.

Advances in Computer Systems Architecture

Advances in Computer Systems Architecture Book
Author : Thambipillai Srikanthan,Jingling Xue
Publisher : Springer Science & Business Media
Release : 2005-10-13
ISBN : 9783540296430
Language : En, Es, Fr & De

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Book Description :

This book constitutes the refereed proceedings of the 10th Asia-Pacific Computer Systems Architecture Conference, ACSAC 2005, held in Singapore in October 2005. The 65 revised full papers presented were carefully reviewed and selected from 173 submissions. The papers are organized in topical sections on energy efficient and power aware techniques, methodologies and architectures for application-specific systems, processor architectures and microarchitectures, high-reliability and fault-tolerant architectures, compiler and OS for emerging architectures, data value predictions, reconfigurable computing systems and polymorphic architectures, interconnect networks and network interfaces, parallel architectures and computation models, hardware-software partitioning, verification, and testing of complex architectures, architectures for secured computing, simulation and performance evaluation, architectures for emerging technologies and applications, and memory systems hierarchy and management.

Advances in Computer Systems Architecture

Advances in Computer Systems Architecture Book
Author : ACSAC (Asia-Pacific Computer Systems Architecture Conference)
Publisher : Springer Science & Business Media
Release : 2004-09-14
ISBN : 3540230033
Language : En, Es, Fr & De

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Book Description :

This book constitutes the refereed proceedings of the 9th Asia-Pacific Computer Systems Architecture Conference, ACSAC 2004, held in Beijing, China in September 2004. The 45 revised full papers presented were carefully reviewed and selected from 154 submissions. The papers are organized in topical sections on cache and memory, reconfigurable and embedded architectures, processor architecture and design, power and energy management, compiler and operating systems issues, application-specific systems, interconnection networks, prediction techniques, parallel architectures and programming, microarchitecture design and evaluation, memory and I/O systems, and others.

VLSI

VLSI Book
Author : Tomasz Wojcicki
Publisher : CRC Press
Release : 2014-10-24
ISBN : 1466599103
Language : En, Es, Fr & De

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Book Description :

Recently the world celebrated the 60th anniversary of the invention of the first transistor. The first integrated circuit (IC) was built a decade later, with the first microprocessor designed in the early 1970s. Today, ICs are a part of nearly every aspect of our daily lives. They help us live longer and more comfortably, and do more, faster. All this is possible because of the relentless search for new materials, circuit designs, and ideas happening on a daily basis at industrial and academic institutions around the globe. Showcasing the latest advances in very-large-scale integrated (VLSI) circuits, VLSI: Circuits for Emerging Applications provides a balanced view of industrial and academic developments beyond silicon and complementary metal–oxide–semiconductor (CMOS) technology. From quantum-dot cellular automata (QCA) to chips for cochlear implants, this must-have resource: Investigates the trend of combining multiple cores in a single chip to boost performance of the overall system Describes a novel approach to enable physically unclonable functions (PUFs) using intrinsic features of a VLSI chip Examines the VLSI implementations of major symmetric and asymmetric key cryptographic algorithms, hash functions, and digital signatures Discusses nonvolatile memories such as resistive random-access memory (Re-RAM), magneto-resistive RAM (MRAM), and floating-body RAM (FB-RAM) Explores organic transistors, soft errors, photonics, nanoelectromechanical (NEM) relays, reversible computation, bioinformatics, asynchronous logic, and more VLSI: Circuits for Emerging Applications presents cutting-edge research, design architectures, materials, and uses for VLSI circuits, offering valuable insight into the current state of the art of micro- and nanoelectronics.

Terrestrial Radiation Effects in ULSI Devices and Electronic Systems

Terrestrial Radiation Effects in ULSI Devices and Electronic Systems Book
Author : Eishi H. Ibe
Publisher : John Wiley & Sons
Release : 2014-11-26
ISBN : 1118479327
Language : En, Es, Fr & De

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Book Description :

This book provides the reader with knowledge on a wide variety of radiation fields and their effects on the electronic devices and systems. The author covers faults and failures in ULSI devices induced by a wide variety of radiation fields, including electrons, alpha-rays, muons, gamma rays, neutrons and heavy ions. Readers will learn how to make numerical models from physical insights, to determine the kind of mathematical approaches that should be implemented to analyze radiation effects. A wide variety of prediction, detection, characterization and mitigation techniques against soft-errors are reviewed and discussed. The author shows how to model sophisticated radiation effects in condensed matter in order to quantify and control them, and explains how electronic systems including servers and routers are shut down due to environmental radiation. Provides an understanding of how electronic systems are shut down due to environmental radiation by constructing physical models and numerical algorithms Covers both terrestrial and avionic-level conditions Logically presented with each chapter explaining the background physics to the topic followed by various modelling techniques, and chapter summary Written by a widely-recognized authority in soft-errors in electronic devices Code samples available for download from the Companion Website This book is targeted at researchers and graduate students in nuclear and space radiation, semiconductor physics and electron devices, as well as other areas of applied physics modelling. Researchers and students interested in how a variety of physical phenomena can be modelled and numerically treated will also find this book to present helpful methods.

CMOS SRAM Circuit Design and Parametric Test in Nano Scaled Technologies

CMOS SRAM Circuit Design and Parametric Test in Nano Scaled Technologies Book
Author : Andrei Pavlov,Manoj Sachdev
Publisher : Springer Science & Business Media
Release : 2008-06-01
ISBN : 1402083637
Language : En, Es, Fr & De

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Book Description :

The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.

Embedded and Networking Systems

Embedded and Networking Systems Book
Author : Gul N. Khan,Krzysztof Iniewski
Publisher : CRC Press
Release : 2013-09-24
ISBN : 1466590653
Language : En, Es, Fr & De

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Book Description :

Embedded and Networking Systems: Design, Software, and Implementation explores issues related to the design and synthesis of high-performance embedded computer systems and networks. The emphasis is on the fundamental concepts and analytical techniques that are applicable to a range of embedded and networking applications, rather than on specific embedded architectures, software development, or system-level integration. This system point of view guides designers in dealing with the trade-offs to optimize performance, power, cost, and other system-level non-functional requirements. The book brings together contributions by researchers and experts from around the world, offering a global view of the latest research and development in embedded and networking systems. Chapters highlight the evolution and trends in the field and supply a fundamental and analytical understanding of some underlying technologies. Topics include the co-design of embedded systems, code optimization for a variety of applications, power and performance trade-offs, benchmarks for evaluating embedded systems and their components, and mobile sensor network systems. The book also looks at novel applications such as mobile sensor systems and video networks. A comprehensive review of groundbreaking technology and applications, this book is a timely resource for system designers, researchers, and students interested in the possibilities of embedded and networking systems. It gives readers a better understanding of an emerging technology evolution that is helping drive telecommunications into the next decade.

Advances in Wireless Mobile Networks and Applications

Advances in Wireless  Mobile Networks and Applications Book
Author : Salah S. Al-Majeed,Chih-Lin Hu,Dhinaharan Nagamalai
Publisher : Springer Science & Business Media
Release : 2011-05-10
ISBN : 3642211526
Language : En, Es, Fr & De

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Book Description :

This book constitutes the refereed proceedings of the Third International Conference on Wireless, Mobile Networks and Applications, WiMoA 2011, and the First International Conference on Computer Science, Engineering and Applications, ICCSEA 2011, held in Dubai, United Arab Emirates, in May 2011. The book is organized as a collection of papers from WiMoA 2011 and ICCSEA 2011. The 8 revised full papers presented in the WiMoA 2011 part were carefully reviewed and selected from 63 submissions. The 20 revised full papers presented in the ICCSEA 2011 part were carefully reviewed and selected from 110 submissions.

Exploring Memory Hierarchy Design with Emerging Memory Technologies

Exploring Memory Hierarchy Design with Emerging Memory Technologies Book
Author : Guangyu Sun
Publisher : Springer Science & Business Media
Release : 2013-09-18
ISBN : 3319006819
Language : En, Es, Fr & De

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Book Description :

This book equips readers with tools for computer architecture of high performance, low power, and high reliability memory hierarchy in computer systems based on emerging memory technologies, such as STTRAM, PCM, FBDRAM, etc. The techniques described offer advantages of high density, near-zero static power, and immunity to soft errors, which have the potential of overcoming the “memory wall.” The authors discuss memory design from various perspectives: emerging memory technologies are employed in the memory hierarchy with novel architecture modification; hybrid memory structure is introduced to leverage advantages from multiple memory technologies; an analytical model named “Moguls” is introduced to explore quantitatively the optimization design of a memory hierarchy; finally, the vulnerability of the CMPs to radiation-based soft errors is improved by replacing different levels of on-chip memory with STT-RAMs.

Fault Tolerant Network on Chip Router Architectures for Multi Core Architectures

Fault Tolerant Network on Chip Router Architectures for Multi Core Architectures Book
Author : Pavan Kamal Sudheendra Poluri
Publisher :
Release : 2014
ISBN :
Language : En, Es, Fr & De

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Book Description :

As the feature size scales down to deep nanometer regimes, it has enabled the designers to fabricate chips with billions of transistors. The availability of such abundant computational resources on a single chip has made it possible to design chips with multiple computational cores, resulting in the inception of Chip Multiprocessors (CMPs). The widespread use of CMPs has resulted in a paradigm shift from computation-centric architectures to communication-centric architectures. With the continuous increase in the number of cores that can be fabricated on a single chip, communication between the cores has become a crucial factor in its overall performance. Network-on-Chip (NoC) paradigm has evolved into a standard on-chip interconnection network that can efficiently handle the strict communication requirements between the cores on a chip. The components of an NoC include routers, that facilitate routing of data between multiple cores and links that provide raw bandwidth for data traversal. While diminishing feature size has made it possible to integrate billions of transistors on a chip, the advantage of multiple cores has been marred with the waning reliability of transistors. Components of an NoC are not immune to the increasing number of hard faults and soft errors emanating due to extreme miniaturization of transistor sizes. Faults in an NoC result in significant ramifications such as isolation of healthy cores, deadlock, data corruption, packet loss and increased packet latency, all of which have a severe impact on the performance of a chip. This has stimulated the need to design resilient and fault tolerant NoCs. This thesis handles the issue of fault tolerance in NoC routers. Within the NoC router, the focus is specifically on the router pipeline that is responsible for the smooth flow of packets. In this thesis we propose two different fault tolerant architectures that can continue to operate in the presence of faults. In addition to these two architectures, we also propose a new reliability metric for evaluating soft error tolerant techniques targeted towards the control logic of the NoC router pipeline. First, we present Shield, a fault tolerant NoC router architecture that is capable of handling both hard faults and soft errors in its pipeline. Shield uses techniques such as spatial redundancy, exploitation of idle resources and bypassing a faulty resource to achieve hard fault tolerance. The use of these techniques reveals that Shield is six times more reliable than baseline-unprotected router. To handle soft errors, Shield uses selective hardening technique that includes hardening specific gates of the router pipeline to increase its soft error tolerance. To quantify soft error tolerance improvement, we propose a new metric called Soft Error Improvement Factor (SEIF) and use it to show that Shield's soft error tolerance is three times better than that of the baseline-unprotected router. Then, we present Soft Error Tolerant NoC Router (STNR), a low overhead fault tolerating NoC router architecture that can tolerate soft errors in the control logic of its pipeline. STNR achieves soft error tolerance based on the idea of dual execution, comparison and rollback. It exploits idle cycles in the router pipeline to perform redundant computation and comparison necessary for soft error detection. Upon the detection of a soft error, the pipeline is rolled back to the stage that got affected by the soft error. Salient features of STNR include high level of soft error detection, fault containment and minimum impact on latency. Simulations show that STNR has been able to detect all injected single soft errors in the router pipeline. To perform a quantitative comparison between STNR and other existing similar architectures, we propose a new reliability metric called Metric for Soft error Tolerance (MST) in this thesis. MST is unique in the aspect that it encompasses four crucial factors namely, soft error tolerance, area overhead, power overhead and pipeline latency overhead into a single metric. Analysis using MST shows that STNR provides better reliability while incurring low overhead compared to existing architectures.

Proceedings

Proceedings Book
Author : N.A
Publisher :
Release : 2007
ISBN :
Language : En, Es, Fr & De

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SBCCI 2007

SBCCI 2007 Book
Author : Antonio Petraglia
Publisher :
Release : 2007
ISBN :
Language : En, Es, Fr & De

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Book Description :